Dr Binu K Mathew

LATEST UPDATES

NAKSHATRA, the annual techno-cultural festival will be organized on Feb. 15-16, 2019
6th edition of SRISHTI, the national level annual project exhibition and competition to be held on Feb. 18-19, 2019

Dr Binu K Mathew

Designation: Professor & HOD
Area: Applied Electronics

Educational Qualifications
PhD in VLSI

PG in Applied Electronics

Professional Experience
Teaching : 16 yrs
Research : 8 yrs

Publications

  • New techniques to enhance FPGA based system security-International Journal for Advanced Research in Computer Engineering and Technology
  • New Logic Module for secured FPGA based system-International Journal of Electronics and Communication Engineering
  • An Area Efficient Asynchronous FPGA Based on Fine Grain Power Gating and Time multiplexed Dual Rail Encoding -IEEE Xplore Digital Library
  • Fixed width Booth Multiplier using Error Compensation-International Journal of Scientific and Engineering Research
  • A fine-grain Power-gated FPGA with an Area efficient High speed time multiplexed level encoded dual rail architecture-International Journal of Scientific and Engineering Research
  • Architecture of a Multi-Functional Programmable Secured Logic Module-International Journal of Applied Engineering Research
  • Design and analysis of a four tap FIR filter using VHDL language-Journal of Science Technology and Management
  • Novel technique to enhance security of reconfigurable circuits-Journal of Theoretical and Applied Information Technology
  • An Efficient Built-in-Test Generation for Hard to Detect Faults Using Adaptable Programmable and Multiple Twisted-Ring Counters-Journal of Science Technology and Management
  • A novel technique to enhance security of logic circuits using a Modified Programmable Secured Logic Module-Middle-East Journal of Scientific Research 
  • Architecture of a PC based System to Enhance Security of Logic Circuits-Journal of Science Technology and Management
  • Design of High Speed Approximate Multiplier with Carry Speculation Compressor-International Journal of Science Technology and Engineering
  • High Speed LUT-SR Family of Random Number Generation-International Journal of Science Technology and Engineering
  • Fault Tolerant Network on-Chip with Priority based Arbiter-International Journal of Science Technology and Engineering
  • VHDL implementation of a direct digital synthesizer for various applications-International Journal of Recent Trends in Engineering & Research
  • Architecture of Self Repairing Logic Systems for Various Fault Tolerant Applications-International Journal of Recent Trends in Engineering & Research
  • Ternary Content Addressable Memory -International Journal of Recent Trends in Engineering & Research
  • Improved Fast Golay Encoder-International Journal of Recent Trends in Engineering & Research-National Conference on Soft Computing, 2006
  • Untestable fault identification in sequential circuits using ILA-ICACS 2007, International Conference 
  • Identification of untestable faults in sequential circuits using ILA-NCVCOM 07, National Conference on VLSI & Communication
  • Fault identification in sequential circuits using ILA-NC(ET)2, National Conference on Emerging Trends in Engineering & Technology
  • High speed matrix multiplier based on two level matrix decomposition-CITICOMS 2007, CIT International Conference on Modeling and Simulation
  • DFT Techniques for Opens in CMOS Latches-ICAC 2008, International Conference on Advances in Computing
  • New techniques for fault detection in Quantum Cellular Automata-International Conference on Emerging Trends in Electronics and Telecommunication
  • An area efficient asynchronous FPGA based on fine-grain power gating and time multiplexed dual rail encoding-iMac4s, 2013
  • A Fine-Grain Power-Gated FPGA with an Area-Efficient High Speed Level-Encoded Dual Rail Architecture-International Conference on Global Innovations in Technologies and Sciences
  • On-chip test generation scheme based on reconfigurable programmable and multiple twisted ring counters-ICCICCT -2014, International Conference on Control, Instrumentation, Communication and Computational Technologies
  • Performance Comparison of an error correction technique in memory-ICCICCT -2014, International Conference on Control, Instrumentation, Communication and Computational Technologies
  • Implementation of a FIR filter model using Reversible Fredkin Gate-International Conference on Control, Instrumentation, Communication and Computational Technologies
  • Design and Implementation of an on-chip test generation scheme based on reconfigurable runtime programmable and multiple twisted ring counters-ICICT-2014, International Conference on Information and Communication Technologies, published in Elsevier Procedia Computer Science
  • Area Efficient High Speed approximate Multiplier with Carry Predictor-International Conference on Emerging Trends in Engineering Science and Technology.
  • Design and performance evaluation of a NoC based router architecture-3rd conference on Solid State Circuits
  • FPGA implementation of high quality random number generators using LUT based shift registers-International Conference on Emerging Trends in Engineering Science and Technology
  • Architecture of coarse grained logic modules for reconfigurable systems-4th conference on Solid state circuits
  • IP Protection using Watermarking with Obfuscation-4th conference on Solid state circuits 
  • Architecture of Tcam using content based address generation-4th conference on Solid state circuits

Contact Details
Mobile: +91 9995496444
Email: binu.k@saintgits.org